1. Field of the Invention
The present invention generally relates to the functional testing of embedded memories, and more particularly relates to a method of and system for functionally testing memories embedded in VLSI devices at enhanced speeds while maintaining a high degree of accuracy.
2. Description of the Prior Art
Developments over the past decade in semiconductor technology have substantially increased the use of Random Access Memories (RAMs) within Very Large Scale Integration (VLSI) devices. Designers realized that a significant increase in system performance can be achieved by placing the RAM structures on the same semiconductor chip as the processing circuitry. In this configuration, RAM accesses can often be made in a single processor clock cycle and therefore significantly increasing system performance.
The strong desire of designers to place RAM structures on the same chip as the processing circuitry becomes readily apparent after analyzing the alternative. If discrete RAM devices are used within a system, the motherboard usually contains a processor chip along with a plurality of RAM devices. When the processor wants to access data from the RAM devices, the processor must send address data through the output buffers of the processor chip, across the board traces, and finally through the input buffers of the RAM chip. There is a relatively large amount of inductance and capacitance on this path due to the semiconductor package (e.g., via bond wires, bond pads, package power planes, package pins, etc) and the board traces. In addition, the delay associated with the input and output buffers of a semiconductor chip can be substantial. Finally, the input buffers of a semiconductor chip typically contain Electric Static Discharge (ESD) diodes which also add capacitance to the path. After the address reach the RAM device, the system must wait for the RAM to access the addressed data. When this is complete, the RAM device drives the data through the RAM output buffers, across the board traces, and through the input buffers of the processor chip. Again, the inductance and capacitance associated with this path can be substantial. This entire process must be completed in one processor clock cycle to have the RAM data available in the next clock cycle. This typically cannot be accomplished for modern processor with high clock rates and therefore places additional pressure on designers to incorporate RAM structures on the same chip as the processing circuitry.
Another unrelated reason why designers strongly prefer to place the RAM structures on the same chip as the processing circuitry is to reduce the pin count in the processor chip. A RAM device has a significant number of I/O signals which must be controlled and observed. The pin count of the processor chip can be substantially reduced by controlling the RAM signals internally and not provide an I/O pin for each.
A final reason for having embedded RAM structures is that often the size of a semiconductor die is determined by the number of I/O pins that must be provided. The size of the die, and hence the cost to produce the die, can often be reduced if the number of I/O pins can be minimized. Furthermore, there are physical packaging limitations which limit the number of I/O pins that are allowed for any given package. These constraints also provide a significant incentive for designers to place RAM structures on the same chip as the processing circuitry.
In the past decade there has been a rapid increase in the number of vendors which offer Application Specific Integrated Circuits (ASICs). ASICs provide a cost effective way of obtaining high speed and high density circuitry that is customized for a specific application. ASICs are semi-custom chips where the customer provides the logic design and the vendor creates the mask layers and performs the fabrication of the chip. The vendor will typically provide the customer with an ASIC library which contains a list of available component which can be used in the logic design of the customer's chip. The reason only a limited number of components are available is that each component must be layed out and simulated by the vendor to ensure proper functionality and performance. In the past decade, many more RAM structures have been added to ASIC libraries for use in customer designs for the reasons stated above. This, coupled with the strong desire to place RAMs on the same chip as the processing circuitry, has created a rapid increase in the number of VLSI devices containing embedded RAM's.
A significant problem created by placing embedded RAM structures within a VLSI device is that the input and output ports of the RAM structure are often not controllable or observable from the external I/O pins of the VLSI device. This makes it very difficult or even impossible to adequately test embedded RAM structures and ensure that they are fully functional. This concern is particularly important in high reliability systems.
Over the past decade, Built-In Self-Test (BIST) techniques have been developed to combat this and other test problems. One method for using BIST for testing on-chip memory is described in U.S. Pat. No. 5,138,619, issued to Fasang et al. Fasang uses a first Pseudo Random Pattern Generator (PRPG) for generating the addresses to the RAM and a second PRPG for generating the data inputs to the RAM. This eliminates the need to directly control the address and data ports of the RAM structure from the external I/O pins of the VLSI device. Fasang also suggests a method for using a Parallel Signature Analyzer (PSA) for creating a signature for the test results and comparing this signature to a known correct signature. A problem with Fasang is that the input test vectors to the RAM structure are random in nature and therefore do not test for some common RAM defects. For example, the method suggested in Fasang would not test for a slow write recovery time problem.
Another method for testing embedded RAM structures is discussed in U.S. Pat. No. 4,715,034 issued to Jacobson. Jacobson suggests using a Pseudo Random Pattern Generator for writing random bits into successive memory cells rather than writing the same bits or fixed sequence of bits into the cells. Jacobson suffers from the same problems as described under Fasang.
A similar method for testing embedded RAM structures is discussed in U.S. Pat. No. 5,173,906 issued to Dreibelbis et al. Dreibelbis suggests a method for using a data pattern generator instead of a PRPG for providing a predetermined set of data patterns to the embedded RAM structure. Dreibelbis also suggests an apparatus which uses conventional Level-Sensitive Scan Design (LSSD) techniques. In accordance with LSSD, Dreibelbis apparently suggests a multi-phase clocking technique for performing the testing algorithm. A problem with the method described by Dreibelbis is that it is complex and relatively difficult to implement in hardware. In addition, the LSSD method does not allow for testing of circuits at actual system speeds because multi-phase clocking is not typically used during functional operation.
Another method for testing embedded RAM structures within a microprocessor is discussed in U.S. Pat. No. 4,873,705 issued to Johnson. The method described in Johnson requires a redundant microprocessor in addition to the microprocessor under test. The redundant microprocessor is used for performing the test algorithm on the microprocessor under test. A problem with the method suggested by Johnson is that a significant amount of support hardware is required to perform the test. In addition, the test sequence suggests by Johnson does not test for a slow write recovery problem.